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C8051T610/1/2/3/4/5/6/7
1. System Overview
C8051T610/1/2/3/4/5/6/7 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted
features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering num-
bers.
?? High-speed
pipelined 8051-compatible microcontroller core (up to 25 MIPS)
?? In-system,
full-speed, non-intrusive debug interface (on-chip)
?? C8051F310 ISP Flash device is available for quick in-system code development
?? 10-bit 500 ksps Single-ended ADC with analog multiplexer and integrated temperature sensor
?? Precision calibrated 24.5 MHz internal oscillator
?? 16 k or 8 k of on-chip Byte-Programmable EPROM—(512 bytes are reserved on 16k version)
?? 1280 bytes of on-chip RAM
C, SPI, and Enhanced UART serial interfaces implemented in hardware
?? SMBus/I
2
?? Four
general-purpose 16-bit timers
?? Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function
?? On-chip Power-On Reset and V DD Monitor
?? On-chip
Voltage Comparators (2)
?? 29/25/21
Port I/O
With on-chip power-on reset, V DD
monitor, watchdog timer, and clock oscillator, the
C8051T610/1/2/3/4/5/6/7 devices are truly stand-alone, system-on-a-chip solutions. User software has
complete control of all peripherals and may individually shut down any or all peripherals for power savings.
Code written for the C8051T610/1/2/3/4/5/6/7 family of processors will run on the C8051F310 Mixed-Sig-
nal ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring spe-
cial emulator circuitry. The C8051T610/1/2/3/4/5/6/7 processors include Silicon Laboratories’ 2-Wire C2
Debug and Programming interface, which allows non-intrusive (uses no on-chip resources), full speed, in-
circuit debugging using the production MCU installed in the final application. This debug logic supports
inspection of memory, viewing and modification of special function registers, setting breakpoints, single
stepping, and run and halt commands. All analog and digital peripherals are fully functional while debug-
ging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging
without occupying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO is used to supply the processor core voltage. The Port I/O and RST pins are tolerant of input
signals up to 5 V. See Table 2.1 for ordering information. Block diagrams of the devices in the
C8051T610/1/2/3/4/5/6/7 family are shown in Figure 1.1, Figure 1.2 and Figure 1.3.
Rev 1.1
15
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